Wide varieties of semiconductor memory devices have been developed. These semiconductor memory devices are continuously employed in new and expanded uses, which require an integrated circuit of increased capabilities and decreased cost. Accordingly, there exists a continuing demand for inexpensive semiconductor devices having increased memory and reduced chip size. Many semiconductor devices are comprised of multiple types of circuits such as memory and logic circuits. Flash memory cells are typically formed, along with other circuits (non-memory circuits) such as core circuits, as embedded flash memory. Flash memory cells may be included in system on a chip (SOC) devices.
Flash memory has become increasingly popular in recent years. A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the flash memory cells is fabricated as a field-effect transistor having a control-gate and a floating-gate. The floating-gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide. The memory cells may be capable of several operations including program, read, write, and erase. For example, memory cells may be electrically charged by injecting electrons from the drain region through the oxide layer onto the floating-gate. The charges may be removed from the floating-gate, in one known approach, by tunneling the electrons to the source through the oxide layer during an erase operation. The data in a memory cell is thus determined by the presence or absence of a charge on the floating-gate.
Amorphous polysilicon (poly) lines or buried lines (for example patterned doped silicon) may be used to interconnect components of the memory cells together in an array. A contact is provided between the poly or buried line and the interconnect structure (typically metal). As arrays become larger, there may be a voltage drop along poly or buried lines. The voltage drop may be detrimental to the function and speed of the array. One method of overcoming this problem may be to use metal lines rather than poly or buried lines to interconnect components of the memory cells. However, a larger memory cell may then be required to accommodate the space needed to connect contacts to each memory cell component.